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integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 pin configuration recommended application: ck409 compliant clock for next gen p4 processor output features: 2 - 0.7v current-mode differential cpu pairs 1 - 0.7v current-mode differential src pair 9 - pci, 3 free running, 33mhz 3 - ref, 14.318mhz 3 - 3v66, 66.66mhz 1 - vch/3v66, selectable 48mhz or 66mhz 2 - 48mhz 1 - 24/48mhz key specifications: cpu/src outputs cycle-cycle jitter < 125ps 3v66 outputs cycle-cycle jitter < 250ps pci outputs cycle-cycle jitter < 250ps +/- 300ppm frequency accuracy on cpu & src clocks programmable timing control hub? for next gen p 4 ? processor functionality features/benefits: quadrom tm frequency selection. programmable output frequency. programmable asynchronous 3v66&pci frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i2c index read/write and block read/write operations. uses external 14.318mhz reference input. supports tight ppm accuracy clocks for serial-ata supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread supports cpu clks up to 400mhz advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. 48-pin ssop bit4 bit3 bit2 bit1 bit0 cpu agp pci fs4fs3fs2fs1fs0 mhz mhz mhz 00000 100.00 66.66 33.33 00001 200.00 66.66 33.33 00010 133.33 66.66 33.33 00011 166.67 66.66 33.33 0 0 1 0 0 200.00 66.66 33.33 00101 400.00 66.66 33.33 00110 266.67 66.66 33.33 00111 333.33 66.66 33.33 01000 100.99 67.33 33.66 01001 201.98 67.33 33.66 01010 134.65 67.33 33.66 01011 168.31 67.32 33.66 01 1 00 115.00 76.66 38.33 01101 230.00 76.66 38.33 01110 153.33 76.66 38.33 01111 191.67 76.66 38.33 1 0000 100.00 66.66 33.33 10001 200.00 66.66 33.33 10010 133.33 66.66 33.33 10011 166.67 71.43 35.71 1 0 1 0 0 200.00 66.66 33.33 10101 400.00 66.66 33.33 10110 266.67 66.66 33.33 10111 333.33 66.66 33.33 11000 105.00 69.99 35.00 11001 210.00 69.99 35.00 11010 140.00 69.99 35.00 11011 175.00 69.99 35.00 11 1 00 110.00 73.33 36.66 11101 220.00 73.33 36.66 11110 146.66 73.33 36.66 11111 183.34 73.33 36.66 note: fs1 and fs0 are equal to intel ck409-defined fsa and fsb, respectively. *fs1/ref0 1 48 vdda *fs0/ref1 2 47 gnd ref2 3 46 iref vddref 4 45 reset# x1 5 44 gnd x2 6 43 cpuclkt1 gnd 7 42 cpuclkc1 **fs2/pciclk_f0 8 41 vddcpu **fs4/pciclk_f1 9 40 cpuclkt0 pciclk_f2 10 39 cpuclkc0 vddpci 11 38 gnd gnd 12 37 srcclkt ^^pciclk0 13 36 srcclkc pciclk1 14 35 vdd pciclk2 15 34 vttpwr_gd/pd# pciclk3 16 33 sdata vddpci 17 32 sclk gnd 18 31 3v66_0 pciclk4 19 30 3v66_1 pciclk5 20 29 gnd **sel24_48#/24_48mhz 21 28 vdd3v66 **fs3/48mhz_0 22 27 3v66_2 48mhz_1 23 26 3v66_3/vch gnd 24 25 vdd48 ^^ an external 2.2k pull-down resistor is needed on this pin ics952607 * this pin have 120k pull-up to vdd ** this pin have 120k pull-down to gnd
2 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 pin description pin # pin name pin type description 1 *fs1/ref0 i/o frequency select latch input pin / 14.318 mhz reference clock. 2 *fs0/ref1 i/o frequency select latch input pin / 14.318 mhz reference clock. 3 ref2 out 14.318 mhz reference clock. 4 vddref pwr ref, xtal power supply, nominal 3.3v 5 x1 in crystal input,nominally 14.318mhz. 6 x2 out crystal output, nominally 14.318mhz 7 gnd pwr ground pin. 8 **fs2/pciclk_f0 i/o frequency select latch input pin / 3.3v pci free running clock output. 9 **fs4/pciclk_f1 i/o frequency select latch input pin / 3.3v pci free running clock output. 10 pciclk_f2 out free running pci clock not affected by pci_stop# . 11 vddpci pwr power supply for pci clocks, nominal 3.3v 12 gnd pwr ground pin. 13 ^^pciclk0 out pci clock output. 14 pciclk1 out pci clock output. 15 pciclk2 out pci clock output. 16 pciclk3 out pci clock output. 17 vddpci pwr power supply for pci clocks, nominal 3.3v 18 gnd pwr ground pin. 19 pciclk4 out pci clock output. 20 pciclk5 out pci clock output. 21 **sel24_48#/24_48mhz i/o latched select input for 24/48mhz output / 24/48mhz clock output. 1=24mhz, 0 = 48mhz. 22 **fs3/48mhz_0 i/o frequency select latch input pin / fixed 48mhz clock output. 3.3v 23 48mhz_1 out 48mhz clock output. 24 gnd pwr ground pin. 25 vdd48 pwr power for 24 & 48mhz output buffers and fixed pll core. 26 3v66_3/vch out 3.3v 66.66mhz clock output / 48mhz vch clock output. 27 3v66_2 out 3.3v 66.66mhz clock output 28 vdd3v66 pwr power pin for the 3v66 clocks. 29 gnd pwr ground pin. 30 3v66_1 out 3.3v 66.66mhz clock output 31 3v66_0 out 3.3v 66.66mhz clock output 32 sclk in clock pin of i2c circuitry 5v tolerant 33 sdata i/o data pin for i2c circuitry 5v tolerant 34 vttpwr_gd/pd# in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active high input. / asynchronous active low input pin used to power down the device into a low power state. 35 vdd pwr power supply, nominal 3.3v 36 srcclkc out complement clock of differential pair for s-ata support. +/- 300ppm accuracy required. 37 srcclkt out true clock of differential pair for s-ata support. +/- 300ppm accuracy required. 38 gnd pwr ground pin. 39 cpuclkc0 out "complementary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 40 cpuclkt0 out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 41 vddcpu pwr supply for cpu clo cks, 3.3v nominal 42 cpuclkc1 out "complementary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 43 cpuclkt1 out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 44 gnd pwr ground pin. 45 reset# out real time system reset signal for frequency gear ratio change or watchdog timer timeout. this signal is active low. 46 iref out this pin establishes the reference current for the cpuclk pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 47 gnd pwr ground pin. 48 vdda pwr 3.3v power for the pll core.
3 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 ics952607 is a 48 pin clock chip following intel ck409 yellow cover specification. this clock synthesizer provides a single chip solution for next generation p4 intel processors and intel chipsets. ics952607 is driven with a 14.318mhz crystal. it generates cpu outputs up to 200mhz. it also provides a tight ppm accuracy output for serial ata suuport. the ics952607 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. m/n control can configure output frequency with resolution up to 0.1mhz increment. this part also provides 128 frequency selections via ics quadrom tm technology as an alternate to m/n programming. general description block diagram power groups vdd gnd 4 7 xtal, ref 28 29 3v66 11,17 12,18 pciclk outputs 35 38 srcclk outputs 41 44 cpu outputs 48 47 mclk, cpu analog, cpu digital 25 24 48mhz fix, fix digital, fix analog description pin number i ref reset# pll2 frequency dividers programmable spread pll1 programmable frequency dividers stop logic 48mhz (1:0) 24_48mhz x1 x2 xtal sdata sclk vttpwrgd# pd# fs (4:0) sel24_48# control logic ref (2:0) cpuclkt (1:0) cpuclkc (1:0) srcclkt srcclkc 3v66 (3:0) pciclk (5:0) pciclk_f (2:0)
4 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 table1: quadrom frequency selection table bit4 bit3 bit2 bit1 bit0 cpu agp pci spread fs4 fs3 fs2 fs1 fs0 mhz mhz mhz % 0 0 0 0 0 0 0 100.00 66.66 33.33 0 to -0.5% down 0 0 0 0 0 0 1 200.00 66.66 33.33 0 to -0.5% down 0 0 0 0 0 1 0 133.33 66.66 33.33 0 to -0.5% down 0 0 0 0 0 1 1 166.67 66.66 33.33 0 to -0.5% down 0 0 0 0 1 0 0 200.00 66.66 33.33 0 to -0.5% down 0 0 0 0 1 0 1 400.00 66.66 33.33 0 to -0.5% down 0 0 0 0 1 1 0 266.67 66.66 33.33 0 to -0.5% down 0000111 333.33 66.66 33.33 0 to -0.5% down 0 0 0 1 0 0 0 100.99 67.33 33.66 0.35% center 0 0 0 1 0 0 1 201.98 67.33 33.66 0.35% center 0 0 0 1 0 1 0 134.65 67.33 33.66 0.35% center 0001011 168.31 67.32 33.66 0.35% center 0 0 0 1 1 0 0 115.00 76.66 38.33 no spread 0 0 0 1 1 0 1 230.00 76.66 38.33 no spread 0 0 0 1 1 1 0 153.33 76.66 38.33 no spread 0001111 191.67 76.66 38.33 no spread 0 0 1 0 0 0 0 100.00 66.66 33.33 0.35% center 0 0 1 0 0 0 1 200.00 66.66 33.33 0.35% center 0 0 1 0 0 1 0 133.33 66.66 33.33 0.35% center 0 0 1 0 0 1 1 166.67 71.43 35.71 0.35% center 0 0 1 0 1 0 0 200.00 66.66 33.33 0.35% center 0 0 1 0 1 0 1 400.00 66.66 33.33 0.35% center 0 0 1 0 1 1 0 266.67 66.66 33.33 0.35% center 0010111 333.33 66.66 33.33 0.35% center 0 0 1 1 0 0 0 105.00 69.99 35.00 no spread 0 0 1 1 0 0 1 210.00 69.99 35.00 no spread 0 0 1 1 0 1 0 140.00 69.99 35.00 no spread 0011011 175.00 69.99 35.00 no spread 0 0 1 1 1 0 0 110.00 73.33 36.66 no spread 0 0 1 1 1 0 1 220.00 73.33 36.66 no spread 0 0 1 1 1 1 0 146.66 73.33 36.66 no spread 0011111 183.34 73.33 36.66 no spread bit6 bit5 table continued on next page.
5 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 table1: quadrom frequency selection table (continued) bit4 bit3 bit2 bit1 bit0 cpu agp pci spread fs4 fs3 fs2 fs1 fs0 mhz mhz mhz % 0 1 0 0 0 0 0 103.00 68.66 34.33 no spread 0 1 0 0 0 0 1 206.00 68.66 34.33 no spread 0 1 0 0 0 1 0 137.33 68.66 34.33 no spread 0 1 0 0 0 1 1 171.67 68.66 34.33 no spread 0 1 0 0 1 0 0 228.89 68.66 34.33 no spread 0 1 0 0 1 0 1 412.00 68.66 34.33 no spread 0 1 0 0 1 1 0 274.67 68.66 34.33 no spread 0100111 343.33 68.66 34.33 no spread 0 1 0 1 0 0 0 105.00 69.99 35.00 no spread 0 1 0 1 0 0 1 210.00 69.99 35.00 no spread 0 1 0 1 0 1 0 140.00 69.99 35.00 no spread 0 1 0 1 0 1 1 175.00 69.99 35.00 no spread 0 1 0 1 1 0 0 233.33 69.99 35.00 no spread 0 1 0 1 1 0 1 420.00 69.99 35.00 no spread 0 1 0 1 1 1 0 280.00 69.99 35.00 no spread 0101111 350.00 69.99 35.00 no spread 0 1 1 0 0 0 0 107.00 71.33 35.66 no spread 0 1 1 0 0 0 1 214.00 71.33 35.66 no spread 0 1 1 0 0 1 0 142.66 71.33 35.66 no spread 0 1 1 0 0 1 1 178.34 71.33 35.66 no spread 0 1 1 0 1 0 0 237.78 71.33 35.66 no spread 0 1 1 0 1 0 1 428.00 71.33 35.66 no spread 0 1 1 0 1 1 0 285.34 71.33 35.66 no spread 0110111 356.66 71.33 35.66 no spread 0 1 1 1 0 0 0 110.00 73.33 36.66 no spread 0 1 1 1 0 0 1 220.00 73.33 36.66 no spread 0 1 1 1 0 1 0 146.66 73.33 36.66 no spread 0 1 1 1 0 1 1 183.34 73.33 36.66 no spread 0 1 1 1 1 0 0 244.44 73.33 36.66 no spread 0 1 1 1 1 0 1 440.00 73.33 36.66 no spread 0 1 1 1 1 1 0 293.34 73.33 36.66 no spread 0111111 366.66 73.33 36.66 no spread bit6 bit5 table continued on next page.
6 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 table1: quadrom frequency selection table 3 (continued) bit4 bit3 bit2 bit1 bit0 cpu agp pci spread fs4 fs3 fs2 fs1 fs0 mhz mhz mhz % 1 0 0 0 0 0 0 95.00 63.33 31.66 no spread 1 0 0 0 0 0 1 190.00 63.33 31.66 no spread 1 0 0 0 0 1 0 126.66 63.33 31.66 no spread 1 0 0 0 0 1 1 158.34 63.33 31.66 no spread 1 0 0 0 1 0 0 211.11 63.33 31.66 no spread 1 0 0 0 1 0 1 380.00 63.33 31.66 no spread 1 0 0 0 1 1 0 253.34 63.33 31.66 no spread 1000111 316.66 63.33 31.66 no spread 1 0 0 1 0 0 0 90.00 59.99 30.00 no spread 1 0 0 1 0 0 1 180.00 59.99 30.00 no spread 1 0 0 1 0 1 0 120.00 59.99 30.00 no spread 1 0 0 1 0 1 1 150.00 59.99 30.00 no spread 1 0 0 1 1 0 0 200.00 59.99 30.00 no spread 1 0 0 1 1 0 1 360.00 59.99 30.00 no spread 1 0 0 1 1 1 0 240.00 59.99 30.00 no spread 1001111 300.00 59.99 30.00 no spread 1 0 1 0 0 0 0 85.00 56.66 28.33 no spread 1 0 1 0 0 0 1 170.00 56.66 28.33 no spread 1 0 1 0 0 1 0 113.33 56.66 28.33 no spread 1 0 1 0 0 1 1 141.67 56.66 28.33 no spread 1 0 1 0 1 0 0 188.89 56.66 28.33 no spread 1 0 1 0 1 0 1 340.00 56.66 28.33 no spread 1 0 1 0 1 1 0 226.67 56.66 28.33 no spread 1010111 283.33 56.66 28.33 no spread 1 0 1 1 0 0 0 80.00 53.33 26.66 no spread 1 0 1 1 0 0 1 160.00 53.33 26.66 no spread 1 0 1 1 0 1 0 106.66 53.33 26.66 no spread 1 0 1 1 0 1 1 133.34 53.33 26.66 no spread 1 0 1 1 1 0 0 177.78 53.33 26.66 no spread 1 0 1 1 1 0 1 320.00 53.33 26.66 no spread 1 0 1 1 1 1 0 213.34 53.33 26.66 no spread 1011111 266.66 53.33 26.66 no spread bit6 bit5 table continued on next page.
7 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 table1: quadrom frequency selection table 4 (continued) bit4 bit3 bit2 bit1 bit0 cpu agp pci spread fs4 fs3 fs2 fs1 fs0 mhz mhz mhz % 1 1 0 0 0 0 0 115.00 76.66 38.33 no spread 1 1 0 0 0 0 1 230.00 76.66 38.33 no spread 1 1 0 0 0 1 0 153.33 76.66 38.33 no spread 1 1 0 0 0 1 1 191.67 76.66 38.33 no spread 1 1 0 0 1 0 0 255.55 76.66 38.33 no spread 1 1 0 0 1 0 1 460.00 76.66 38.33 no spread 1 1 0 0 1 1 0 306.67 76.66 38.33 no spread 1100111 383.33 76.66 38.33 no spread 1 1 0 1 0 0 0 115.00 79.99 40.00 no spread 1 1 0 1 0 0 1 230.00 79.99 40.00 no spread 1 1 0 1 0 1 0 153.33 79.99 40.00 no spread 1 1 0 1 0 1 1 191.67 79.99 40.00 no spread 1 1 0 1 1 0 0 255.55 79.99 40.00 no spread 1 1 0 1 1 0 1 460.00 79.99 40.00 no spread 1 1 0 1 1 1 0 306.67 79.99 40.00 no spread 1101111 383.33 79.99 40.00 no spread 1 1 1 0 0 0 0 78.00 51.99 26.00 no spread 1 1 1 0 0 0 1 156.00 51.99 26.00 no spread 1 1 1 0 0 1 0 104.00 51.99 26.00 no spread 1 1 1 0 0 1 1 130.00 51.99 26.00 no spread 1 1 1 0 1 0 0 173.33 51.99 26.00 no spread 1 1 1 0 1 0 1 312.00 51.99 26.00 no spread 1 1 1 0 1 1 0 208.00 51.99 26.00 no spread 1110111 260.00 51.99 26.00 no spread 1 1 1 1 0 0 0 75.00 50.00 25.00 no spread 1 1 1 1 0 0 1 150.00 50.00 25.00 no spread 1 1 1 1 0 1 0 100.00 50.00 25.00 no spread 1 1 1 1 0 1 1 125.00 50.00 25.00 no spread 1 1 1 1 1 0 0 166.67 50.00 25.00 no spread 1 1 1 1 1 0 1 300.00 50.00 25.00 no spread 1 1 1 1 1 1 0 200.00 50.00 25.00 no spread 1111111 250.00 50.00 25.00 no spread bit6 bit5
8 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 i 2 c table: frequency select register control function bit 7 fs source frequency h/w iic select rw 0 bit 6 fs6 freq select bit 6 rw 0 bit 5 fs5 freq select bit 5 rw 0 bit 4 fs4 freq select bit 4 rw 0 bit 3 fs3 freq select bit 3 rw 0 bit 2 fs2 freq select bit 2 rw 0 bit 1 fsa freq select bit 1 rw 0 bit 0 fsb freq select bit 0 rw 0 i 2 c table: spreading and device behavior control register control function bit 7 ss1 spread select 1 rw 0 bit 6 ss0 spread select 0 rw 0 bit 5 ss_en spread enable control rw 1 bit 4 wds_en wd soft reset enable rw 0 bit 3 src/src# output control rw 1 bit 2 reserved reserved rw 1 bit 1 cpuclkt/c_1 output control rw 1 bit 0 cpuclkt/c_0 output control rw 1 i 2 c table: output control register control function bit 7 src stop mode 0: srct driven during pd#; 1: tri-stated rw 0 bit 6 reserved reserved rw 0 bit 5 cput stop mode 0: cput driven during pd#; 1: tri-stated rw 0 bit 4 reserved reserved rw 0 bit 3 3v66_2 output control rw 1 bit 2 reserved reserved rw 1 bit 1 reserved reserved rw 1 bit 0 reserved reserved rw 1 -- -- -- disable enable -- -- driven hi-z driven hi-z -- disable disable enable enable on off disable enable 01 = 0.50% 11 = no spread - - 27 - - - type pwd 40,39 byte 2 pin # name 0 1 - 37,36 - 43,42 on off - pwd - - byte 1 pin # name type 00 = 0.35% 10 = 0.75% - - see table 1: quadrom frequency selection table 01 pwd - byte 0 pin # name type latch inputs iic 01 - - - - - - -
9 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 i 2 c table: output control register control function bit 7 asel1 3v66/pci freq select rw 0 bit 6 reserved reserved rw 0 bit 5 pciclk5 output control rw 1 bit 4 pciclk4 output control rw 1 bit 3 pciclk3 output control rw 1 bit 2 pciclk2 output control rw 1 bit 1 pciclk1 output control rw 1 bit 0 pciclk0 output control rw 1 disable enable see table 5: async agp/pci freq table -- disable enable disable enable disable enable disable enable disable enable pwd - byte 3 pin # name type 0 1 - 20 19 16 15 14 13 table 3: linear m/n agp/pci programmable frequency example c 31 65.15 32.58 c 33 67.44 33.72 b 2d 65.24 32.62 7 1e 67.57 33.78 a 29 65.34 32.67 b 2f 67.70 33.85 7 1d 65.79 32.89 a 2b 68.01 34.01 6 19 66.01 33.01 c 34 68.58 34.29 d 36 66.14 33.07 b 30 68.93 34.47 c 32 66.30 33.15 a 2c 69.34 34.67 b 2e 66.47 33.24 c 35 69.73 34.86 a 2a 66.68 33.34 9 28 69.83 34.91 d 37 67.21 33.61 6 1b 70.01 35.01 hex b5b3:0 hex b6b6:0 agp freq pci freq hex b5b3:0 hex b6b6:0 agp freq pci freq i 2 c table: output control register control function bit 7 48mhz_0 2x output drive 0=2x drive rw 0 bit 6 srcfs src frequency select -0 bit 5 reserved reserved rw 0 bit 4 3v66_1 output control rw 1 bit 3 3v66_0 output control rw 1 bit 2 pciclk_f2 output control rw 1 bit 1 pciclk_f1 output control rw 1 bit 0 pciclk_f0 output control rw 1 i 2 c table: reserved register control function bit 7 3v66_3/vch select output select rw 0 bit 6 mode sel1 rw 0 bit 5 mode sel0 rw 0 bit 4 3v66_3/vch output control rw 1 bit 3 m pll2 div3 rw x bit 2 m pll2 div2 rw x bit 1 m pll2 div1 rw x bit 0 m pll2 div0 rw x 3v66 vch see table 4: mode selection table disable enable disable enable disable enable disable enable disable enable 100mhz 200mhz disable enable -- the decimal representation of m pll2 div (3:0) + 2 is equal to ref divider value for pll2 01 01 - - - - pwd 8 byte 5 pin # name type pwd 2x drive normal name type byte 4 pin # pll mode selection bits m divider programming bits for async mode 2&3 26 - - 30 31 10 9 -
10 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 table 4: mode selection table mode standard overclock mode cpu overclock mode graphic overclock mode iic control byte 5 bit(6:5) = 00 byte 5 bit(6:5) = 01 byte 5 bit(6:5) = 10 cpu m/n overclocking byte 11 & 12 byte 11 & 12 byte 11 & 12 src m/n overclocking byte 11 & 12 byte 5 & 6 (asynchronous) byte 11 & 12 agp/pci m/n overclocking byte 11 & 12 byte 5 & 6 (asynchronous) byte 5 & 6 (asynchronous) spreading all clocks have spread. only cpu clocks have spread. latch input shoud be set as fs(4:0) = 10xxx. cpu & src have spread. remark all clocks oveclock together by byte 11&12 m/n programming. cpu overclock by byte 11&12 src/agp/pci overclock by byte 5&6 asynchronously. cpu/src overclock by byte 11&12 agp/pci overclock by byte 5&6 asynchronously. mode b (b6&b3 bit 7) agp/pci can be selected to be overclock from 66/33, 72/36 or 80/40. simple async agp/pci overclocking w/o using m/n programming. src can be kept at 100 w/o spread yet agp/pci can be overclocked. simple async agp/pci overclocking w/o using m/n programming. table 5: asynchronous 3v66/pci frequency table byte6 bit7 byte3 bit7 3v66/pci frequency 0 0 66.66/33.33 0 1 80.00/40.00 1 0 72.73/36.36 i 2 c table: vendor & revision id register control function bit 7 asel0 3v66/pci freq select rw 0 bit 6 n pll2 div6 rw x bit 5 n pll2 div5 rw x bit 4 n pll2 div4 rw x bit 3 n pll2 div3 rw x bit 2 n pll2 div2 rw x bit 1 n pll2 div1 rw x bit 0 n pll2 div0 rw x i 2 c table: vendor & revision id register control function bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 -- -- -- -- -- 1 -- -- -- the decimal representation of n pll2 div (6:0) + 8 is equal to vco divider value for pll2. 01 byte 6 pin # name - - - pwd - - n divider programming bits for async mode 2&3 - - - see table 4: async agp/pci freq table - type - vendor id - - pwd - revision id - - - byte 7 pin # name 0 type
11 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 i 2 c table: byte count register control function bit 7 bc7 rw 0 bit 6 bc6 rw 0 bit 5 bc5 rw 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 1 bit 1 bc1 rw 1 bit 0 bc0 rw 1 i 2 c table: watchdog timer register control function bit 7 wd7 wd timer bit 7 rw 0 bit 6 wd6 wd timer bit 6 rw 0 bit 5 wd5 wd timer bit 5 rw 0 bit 4 wd4 wd timer bit 4 rw 0 bit 3 wd3 wd timer bit 3 rw 1 bit 2 wd2 wd timer bit 2 rw 0 bit 1 wd1 wd timer bit 1 rw 1 bit 0 wd0 wd timer bit 0 rw 1 i 2 c table: vco control select bit & wd timer control register control function bit 7 m/nen m/n programming enable rw 0 bit 6 wden watchdog enable r 1 bit 5 wdfsen wd safe frequency mode rw 0 bit 4 wd sf4 rw 0 bit 3 wd sf3 rw 0 bit 2 wd sf2 rw 0 bit 1 wd sf1 rw 0 bit 0 wd sf0 rw 0 i 2 c table: vco frequency control register control function bit 7 n div8 n divider prog bit 8 rw x bit 6 m div6 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x pwd 01 01 disable enable pwd 1 01 writing to this register will configure how many bytes will be read back, default is 0f = 15 bytes. 0 byte 9 pin # name type disable enable latched fs/byte0 these bits represent x*290ms the watchdog timer waits before it goes to alarm mode. default is 11 x 293ms = 3.2s. writing to these bit will configure the safe frequency as byte0 bit (4:0). the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(8:0)+8] / [mdiv(6:0)+2] wd b10 b(4:0) - m divider programming bits - - - - - - - byte 11 pin # name type - watch dog safe freq programming bits - - - - - - pwd - byte 10 pin # name type - - - - - pwd - byte count programming b(7:0) - - - - - - - type name byte 8 pin # - - -
12 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 i 2 c table: vco frequency control register control function bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x i 2 c table: spread spectrum control register control function bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x i 2 c table: spread spectrum control register control function bit 7 reserved reserved r 0 bit 6 reserved reserved r 0 bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x i 2 c table: output divider control register control function bit 7 src div3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 6 src div2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 5 src div1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 4 src div0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x bit 3 cpu div3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 2 cpu div2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 1 cpu div1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 0 cpu div0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x 01 01 0 these spread spectrum bits in byte 13 and 14 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. these spread spectrum bits in byte 13 and 14 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. 01 -- -- 1 the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(8:0)+8] / [mdiv(6:0)+2] - cpudivider ratio programmaing bits - - - pwd - src divider ratio programmaing bits - - - byte 15 pin # name type - - spread spectrum programming b(13:8) - - - - - pwd - byte 14 pin # name type pwd - spread spectrum programming b(7:0) - - - - - - - name type - - byte 13 pin # pwd - n divider programming b(8:0) - - - - - byte 12 pin # name type
13 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 i 2 c table: output divider control register control function bit 7 reserved reserved rw x bit 6 reserved reserved rw x bit 5 reserved reserved rw x bit 4 reserved reserved rw x bit 3 3v66div3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 2 3v66div2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 1 3v66div1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 0 3v66div0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x i 2 c table: output divider control register control function bit 7 reserved reserved rw x bit 6 3v66inv 3v66 phase invert rw x bit 5 srcinv src phase invert rw x bit 4 cpuinv cpu phase invert rw x bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 0 i 2 c table: group skew control register control function bit 7 reserved reserved rw 0 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 0 i 2 c table: group skew control register control function bit 7 3v66skw3 rw 0000:0 0100:150 1000:300 1100:450 0 bit 6 3v66skw2 rw 0001:n/a 0101:n/a 1001:n/a 1101:600 0 bit 5 3v66skw1 rw 0010:n/a 0110:n/a 1010:n/a 1110:750 0 bit 4 3v66skw0 rw 0011:n/a 0111:n/a 1011:n/a 1111:900 0 bit 3 pciskw3 rw 0000:0 0100:150 1000:300 1100:450 1 bit 2 pciskw2 rw 0001:n/a 0101:n/a 1001:n/a 1101:600 1 bit 1 pciskw1 rw 0010:n/a 0110:n/a 1010:n/a 1110:750 0 bit 0 pciskw0 rw 0011:n/a 0111:n/a 1011:n/a 1111:900 0 -- -- -- -- -- -- -- default default inverse inverse -- -- -- -- default inverse -- -- 1 -- 01 01 cpu-pci 7 step skew control (ps) - - pin # pin # - - - - - - - - - pwd - cpu-3v66 7 step skew control (ps) - - - byte 19 name type - - - - pwd - name type 0 1 -- byte 18 - - - pwd - byte 17 pin # name type 0 - 3v66 divider ratio programmaing bits - - - pwd - name type -- -- - - - byte 16 pin #
14 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 i 2 c table: group skew control register control function bit 7 pciskw3 rw 0000:0 0100:150 1000:300 1100:450 1 bit 6 pciskw2 rw 0001:n/a 0101:n/a 1001:n/a 1101:600 1 bit 5 pciskw1 rw 0010:n/a 0110:n/a 1010:n/a 1110:750 0 bit 4 pciskw0 rw 0011:n/a 0111:n/a 1011:n/a 1111:900 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 0 i 2 c table: slew rate control register control function bit 7 pcifstr1 1 bit 6 pcifstr0 1 bit 5 reserved reserved rw 1 bit 4 reserved reserved rw 1 bit 3 reserved reserved rw 1 bit 2 reserved reserved rw 1 bit 1 agpstr1 rw 1 bit 0 agpstr0 rw 1 i 2 c table: slew rate control register control function bit 7 rw 1 bit 6 rw 0 bit 5 pcifstr1 1 bit 4 pcifstr0 1 bit 3 pcifstr1 1 bit 2 pcifstr0 1 bit 1 pcifstr1 1 bit 0 pcifstr0 1 i 2 c table: output control register control function bit 7 48mhz_0 output control rw 1 bit 6 24_48mhz output control rw 1 bit 5 ref1 output control rw 1 bit 4 ref0 output control rw 1 bit 3 ref2 output control rw 1 bit 2 48mhz_1 output control rw 1 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 0 -- enable disable enable -- - disable enable disable enable 01 01 = 0.75x 11 = 1.00x 00 = 0.63x -- type pwd disable enable disable enable disable pwd 01 01 -- -- - byte 20 pin # name type 0 1 01 = 0.75x 10 = 0.88x -- 00 = 0.70x 10 = 0.90x 11 = 1.00x -- - - - byte 23 pin # - - - - - - - - - - - - - - pwd agpclk strength control - byte 22 pin # name - pwd - pciclkf (2:0) strength control - byte 21 pin # name type rw 00 = 0.63x cpu-pci f(2:0) 7 step skew control (ps) - - - name - 3 21 2 1 23 - - pciclk (1:0) strength control 00 = 0.63x - -- 01 = 0.80x 11 = 1.00x 01 = 0.75x 11 = 1.00x 22 type rw 00 = 0.63x 10 = 0.88x ref_slw ref slew rate control pciclk (5) strength control 00 = medium 10 = strong 01 = weak 11 = n/a 10 = 0.88x pciclk (4:2) strength control 10 = 0.88x 01 = 0.75x 11 = 1.00x rw rw
15 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 i 2 c table: read back register control function bit 7 wdhrb wd hard alarm status read back rx bit 6 wdsrb wd soft alarm status read back rx bit 5 reserved reserved r 0 bit 4 fs4rb fs4 read back r x bit 3 fs3rb fs3 read back r x bit 2 fs2rb fs2 read back r x bit 1 fsarb fsa read back r x bit 0 fsbrb fsb read back r x -- -- -- -- -- -- -- -- 01pwd type byte 24 - - - - pin # - - name - -
16 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
17 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3v +/-5% 2 v dd + 0.3 v input mid voltage v mi d 3.3v +/-5% 1 1.8 v input low voltage v il 3.3v +/-5% v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ua i il1 v in = 0 v; inputs with no pull- up resistors -5 ua i il2 v in = 0 v; inputs with pull-up resistors -200 ua operating supply current i dd3.3op full active, c l = full load; 350 ma all diff pairs driven 35 ma all differential pairs tri-stated 12 ma input frequency 3 f i v dd = 3.3 v 14.31818 mhz 3 pin inductance 1 l p in 7nh1 c in logic inputs 5 pf 1 c ou t output pin capacitance 6 pf 1 c inx 4 x1 & x2 pins 5 pf 1 clk stabilization 1,2 t stab from vdd power-up or de- assertion of pd# to 1st clock. 1.8 ms 1,2 modulation frequency triangular modulation 30 33 khz 1 1 guaranteed by design, not 100% tested in production. 2 see timin g dia g rams for timin g requirements. input low current powerdown current 4 crystal recommendations: c l = 20pf and shunt cap. max = 5pf. i dd3.3pd 3 input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. input capacitance 1 absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. core supply voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd + 0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c
18 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 electrical characteristics - cpu & src 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3v +/-5%; c l =2pf parameter symbol conditions min typ max units notes current source output impedance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 850 1 voltage low vlow -150 150 1 max volta g e vovs 1150 1 min voltage vuds -300 1 crossing voltage (abs) vcross(abs) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all edges 140 mv 1 lon g accurac y ppm see tperiod min-max values -300 300 ppm 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 v t = 50% 100 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 125 ps 1 1 guaranteed by design, not 100% tested in production. src clock outputs run at only 100mhz or 200mhz, specs for 133.33 and 166.66 do not apply to src clock pair. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv
19 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma ed g e rate risin g ed g e rate 1 4 v/ns 1 edge rate falling edge rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 250 ps 1 jitter t jcyc-cyc v t = 1.5 v 3v66 250 ps 1 1 guaranteed by design, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh output low current i ol electrical characteristics - pciclk t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y ppm see tperiod min-max values -300 300 ppm 1,2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol@min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma edge rate rising edge rate 1 4 v/ns 1 edge rate falling edge rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 500 ps 1 jitter t jcyc-cyc v t = 1.5 v 3v66 250 ps 1 1 guaranteed by design, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh output low current i ol
20 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 electrical characteristics - vch, 48mhz, 24mhz t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -200 200 ppm 1,2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma edge rate rising edge rate 1 2 v/ns 1 edge rate falling edge rate 1 2 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 1 ns 1 long term jitter 125us period jitter (8khz frequency modulation amplitude) 6ns1 1 guaranteed b y desi g n, not 100% tested in production. output low current i ol 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref out p ut is at 14.31818mhz output high current i oh electrical characteristics - ref-14.318mhz t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1 output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 2 ns 1 fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns 1 skew t sk1 1 v t = 1.5 v 500 ps 1 duty cycle d t1 1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc 1 v t = 1.5 v 1000 ps 1 1 guaranteed by design, not 100% tested in production.
21 integrated circuit systems, inc. ics952607 advance information 0734?07/16/04 ordering information ics952607 y flf-t index area index area 1 2 n d h x 45 e1 e seating plane seating plane a1 a e - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) example: designation for tape and reel packaging lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf- t

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